This invention relates to digital computers and digital data processors having control sections which are driven by microprograms stored in storage units also located in such computers and processors. Such microprograms are made up of microwords which are used in a sequential manner to control the various elemental operations performed within the computer or data processor.
As is known, efforts are continually being made to improve the performance and reduce the cost of data processors. Unfortunately, the methods available for accomplishing these objectives are frequently in conflict with one another. In general, the instruction processing speed in a data processor can be improved by using more hardware. This, however, increases the cost. What is usually sought, therefore, is a compromise which will improve the performance to cost ratio of the processor.
These considerations are particularly applicable to the case of the control section in a microprogrammed data processor. In particular, the instruction processing speed can usually be increased by increasing the length (number of bits) of the microwords which drive the control section. This is because the increased number of bits enables a greater number of control actions or elemental operations to be performed by each microword. This, however, increases the cost because more control lines, more integrated circuit input/output connections and more control hardware is required to implement the increased number of control operations.
Conversely, the cost can be reduced by decreasing the bit length of the microwords. This, however, usually results in a reduced instruction processing speed. The smaller number of bits per microword means that fewer different kinds of elemental operations are possible. This, in turn, means that the operations which are available must be used a greater number of times in order to accomplish the same result. In other words, a greater number of microwords and, hence, a greater number of sequential microword cycles must be used to accomplish the same result. This reduces the instruction processing speed and, hence, the performance.
Prior workers in the data processor art have recognized the desirability of building a better microprogrammed control section. Thus, various and sundry proposals have been heretofore made for reducing the amount of control section hardware, for increasing the flexibility of the control actions or for modifying the control section to reduce the overall processing time for the machine macroinstructions. Some of these proposals appear to achieve some net improvement, while others do not. Some achieve increased speed or flexibility but at increased cost. And some simplify the control section in one area but complicate it in another.
One class of prior art proposals is represented by the above-cited Rakoczi et al and Mock et al U.S. patents and the IBM Deutschland GmbH German patent application. These proposals seek to reduce the number of separate microword sequences or microroutines that are required to be stored in the control storage apparatus by providing one or more so-called "universal" microroutines, each of which is capable of executing a number of different machine macroinstructions. In other words, a single common microroutine is provided for a group of machine microinstructions which differ only in certain minor respects. Auxiliary hardware is then provided for detecting which macroinstruction is to be processed and for modifying one or more bits in the microwords to take into account the minor differences between the grouped macroinstructions. These proposals have the advantage of reducing the total amount of storage space required to store the total set of miroroutines, but have the disadvantage of requiring the additional hardware for taking into account the macroinstruction differences. Also, these proposals do not increase the instruction processing speed because the number of bits in each microword remains the same and, hence, the limit on the number of independent control actions remains the same.
The above-cited Tessera et al patent describes a method which allegedly enables a reduction in the length of the microwords without substantially reducing the number of independent control actions. This is accomplished by means of a hardwired sequencer which sits alongside of the control store holding the microwords and is controlled by the same microword address bits which are used to address the control store. When certain microwords are addressed, the hardwired sequencer is activated to provide additional control signals. This does appear to reduce the microword length and, hence, the over-all size of the control store, but with the added expense of providing a relatively complicated hardwired sequencer. Also, this method appears to be of somewhat limited flexibility in that the additional control signals provided by the hardwired sequencer are directly related to the particular microword being addressed.
The above-cited patent to Shapiro describes certain hardware for speeding up the macroinstruction fetching operations which constitute part of each microroutine performed by the processor. This is a desirable objective but the described additional hardware for accomplishing same is somewhat complicated and costly. More importantly, the described technique relates only to the fetching and not to the execution of macroinstructions. Thus, the improvement in performance is somewhat limited.
The cited Ottaway et al and Schwartz patents and the Hitt et al technical article describe further proposals for modifying the conventional construction of a microprogrammed control section. Ottaway et al describe the use of auxiliary hardware for modifying the next address field in microwords employing such fields. Hitt et al describe a mechanism for selectively modifying the bits in the microwords as they are set into the control register. Schwartz describes an adaptive microword decoding arrangement wherein a first group of bits in a microword are used to select the elemental microoperations to be controlled by a second group of bits in the microword. These proposals also have various advantages and disadvantages. They are, however, of generally limited applicability and do not solve the need for a relatively inexpensive mechanism which can be used in various types of processors for improving the performance/cost ratio thereof.
The above-cited prior art represents what applicants presently consider to be the best of the prior art presently known to them. No representation is made or intended, however, that better prior art does not exist. Nor is any representation made or intended that the foregoing interpretations are the only interpretations that can be placed on this prior art.